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A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector

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11 Author(s)
Nosaka, H. ; NTT Photonics Labs., NTT Corp., Atsugi, Japan ; Sano, E. ; Ishii, K. ; Ida, M.
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We describe a 40-Gbit/s-class clock and data recovery (CDR) circuit with an extremely wide pull-in range. A Darlington-type voltage-controlled oscillator (VCO) is newly designed to cover the STM-256/OC-768 full-rate-clock frequencies with a wide frequency margin. We also describe a new lock detector using an exclusive-NOR gate. The CDR IC was fabricated using InP/InGaAs HBTs. Error-free operation and wide eye opening were confirmed for 40-, 43-, and 45-Gbit/s PRBS with a word length of 231 - 1. We attached a frequency search and phase control (FSPC) circuit to the chip as a new frequency acquisition aid, and this allows the CDR circuit to pull in throughout a 39-45-Gbit/s range. The peak-to-peak and rms jitter of the recovered clock were 3.6 and 0.48 ps, respectively.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:39 ,  Issue: 8 )