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A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO2 by using HfN replacement gate

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9 Author(s)
Ren, C. ; Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore ; Yu, H.Y. ; Kang, J.F. ; Wang, X.P.
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A replacement gate process employing a HfN dummy gate and sub-1-nm equivalent oxide thickness (EOT) HfO2 gate dielectric is demonstrated. The excellent thermal stability of the HfN-HfO2 gate stack enables its use in high temperature CMOS processes. The replacement of HfN with other metal gate materials with work functions adequate for n- and pMOS is facilitated by a high etch selectivity of HfN with respect to HfO2, without any degradation to the EOT, gate leakage, or time-dependent dielectric breakdown characteristics of HfO2. By replacing the HfN dummy gate with Ta and Ni in nMOS and pMOS devices, respectively, a work function difference of ∼0.8 eV between nMOS and pMOS gate electrodes is achieved. This process could be applicable to sub-50-nm CMOS technology employing ultrathin HfO2 gate dielectric.

Published in:

Electron Device Letters, IEEE  (Volume:25 ,  Issue: 8 )