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Effect of capping silicon nitride layer and nitrided gate oxide on hump of transistors

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3 Author(s)
Park, W.K. ; Hynix Semicond. Inc., Cheongju-Si, South Korea ; Lee, J.H. ; Lim, G.

In this letter, we investigate the effect of capping silicon nitride and nitrided gate oxide on the hump in the sub-threshold slope of various transistors. Silicon wafers having both high- and low-voltage transistors are fabricated. The thin gate oxide is grown by nitric oxidation, while two step process of dry oxidation and low-pressure chemical vapor deposition (LPCVD) is used for the thick gate oxide. Note that the thickness of thin gate oxide is 4.5 nm, and 29 nm for thick gate oxide. It appears that both low-voltage nMOS and pMOS do not show any hump, nor does high-voltage pMOS. The subthreshold hump of high-voltage nMOS depends on process conditions. It shows severe hump without capping silicon nitride layer due to moisture diffusion during thermal anneal after interlayer oxide deposition by LPCVD. It also appears that nitrided oxide is effective to prevent hump by stopping moisture diffusion.

Published in:

Electron Device Letters, IEEE  (Volume:25 ,  Issue: 8 )