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A built-in parametric timing measurement unit

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3 Author(s)
Ming-Jun Hsiao ; Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Jing-Reng Huang ; Tsin-Yuan Chang

On-chip timing-measurement units are needed because accessibility to internal nodes in SoCs is very limited, and performing time interval measurements using automatic test equipment is very difficult and expensive. We present a parametric timing measurement solution, which uses self-timed techniques and delivers high linearity and improved accuracy, at low risk of measurement error. Performing the time-to-digital conversion via built-in circuitry allows accurate measurement of short time intervals and setup/hold time. This circuitry coordinates well with low-cost ATE. To achieve this solution, researchers have used techniques such as delay matrices, phase-locked loops (PLLs), and dual-slope conversion.

Published in:

Design & Test of Computers, IEEE  (Volume:21 ,  Issue: 4 )