Referenced Items are not available for this document.
We present a real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images in future spaceborne systems. In particular, we discuss the integrated design approach, from top-level algorithm specifications and system requirements, design methodology, functional verification and performance validation, down to hardware design and implementation.
Published in:
Radar Conference, 2004. Proceedings of the IEEE
Date of Conference: 26-29 April 2004
- Page(s):
- 15 - 20
- Print ISBN:
- 0-7803-8234-X
- INSPEC Accession Number:
- 7972406
- Digital Object Identifier :
- 10.1109/NRC.2004.1316388
- Product Type:
- Conference Publications
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