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Onboard FPGA-based SAR processing for future spaceborne systems

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14 Author(s)
C. Le ; Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA ; S. Chan ; F. Cheng ; W. Fang
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We present a real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images in future spaceborne systems. In particular, we discuss the integrated design approach, from top-level algorithm specifications and system requirements, design methodology, functional verification and performance validation, down to hardware design and implementation.

Published in:

Radar Conference, 2004. Proceedings of the IEEE

Date of Conference:

26-29 April 2004