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Formal verification of timed systems: a survey and perspective

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1 Author(s)
Farn Wang ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

An overview of the current state of the art of formal verification of real-time systems is presented. We discuss commonly accepted models, specification languages, verification frameworks, state-space representation schemes, state-space construction procedures, reduction techniques, pioneering tools, and finally some new related issues. We also make a few comments according to our experience with verification tool design and implementation.

Published in:

Proceedings of the IEEE  (Volume:92 ,  Issue: 8 )