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Multiple channel programmable timing generators with single cyclic delay line

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3 Author(s)
Ting-Yuan Wang ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Shih-Min Lin ; Hen-Wai Tsao

In this paper, we present the design and measurement results of multiple channel programmable timing generators (TGs) using single cyclic delay line for high-speed automatic test equipment (ATE) with 37.5 ps resolution and 5 ms programmable delay range. There are three TGs, and each one consists of a 19-bit 360-MHz count-up counter, a 19-bit cycle comparator, a zero cycle detector, a control word splitter, and an output selector with an 8X-interpolator. A 32-stage cyclic delay line is constructed via a pulsewidth self-controlled delay cell (PWSCDC). The proposed timing generator uses the TSMC 0.35 μm 1P4M process with a die size of 2.33 mm ×2.17 mm. The dynamic nonlinearity (DNL) is less than ±0.6 LSB (37.5 ps). The integral nonlinearity (INL) is between -1 LSB and 7 LSB before calibration, and is between ±0.4 LSB after root-mean-square (rms) value calibration. The multichannel phase mismatch (MCPM) is 19 ps (rms), and jitter is 13.7 ps (rms).

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Instrumentation and Measurement, IEEE Transactions on  (Volume:53 ,  Issue: 4 )