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A novel multiplexer-based low-power full adder

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5 Author(s)
Yingtao Jiang ; Dept. of Electr. & Comput. Eng., Univ. of Nevada, Las Vegas, NV, USA ; Al-Sheraidah, A. ; Wang, Yuke ; Sha, E.
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The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF and 10T ) and is 64% faster.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:51 ,  Issue: 7 )

Date of Publication:

July 2004

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