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Both trap generation and Stress-Induced Leakage Current (SILC) are measured as a function of the stress voltage on a 1nm/4nm SiO2/HfO2 stack. The SILC firstly rises proportionally with the bulk trap density in the HfO2 but close to breakdown this relation becomes quadratic, indicating that first single-trap conduction paths are causing the SILC, later followed by two-trap conduction paths. At stress conditions, the SILC adds tip to two decades to the initial leakage current. At elevated temperature, the leakage current increase is even higher. At room temperature, however, the SILC poses no reliability restriction for logic CMOS applications.