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Design and implementation of a parameterizable LDPC decoder IP core

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5 Author(s)
Murphy, G. ; Dept. of Microelectron. Eng., Univ. Coll. Cork, Ireland ; Popovici, E.M. ; Bresnan, R. ; Marnane, W.P.
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This paper presents a design methodology that quickly enables the design and implementation of a fully parallel log-domain LDPC decoder based on any parity check matrix. A simulation method to perform an analysis of an arbitrary LDPC code is presented and then extended to predict the actual performance of the final hardware implementation. The design trade-offs due to parameterizable terms such as message resolution and approximation of the log functions are discussed. Finally using the presented design methodology an IP core is generated (using a randomly chosen parity check matrix H). Results for this IP core are presented for an ASIC implementation using a 0.35 μm CMOS technology.

Published in:

Microelectronics, 2004. 24th International Conference on  (Volume:2 )

Date of Conference:

16-19 May 2004