Algorithms and architecture for the L1 calorimeter trigger at D0 run IIb

This paper presents the algorithms and the architecture proposed for the upgrade of the level 1 calorimeter trigger for the D0 experiment. We describe the digital-signal-processing algorithm applied to individual trigger tower signals and the physics algorithms that process the complete array of trigger towers. We investigate the performance of these algorithms and justify our choices. We present the hardware architecture of the system designed to analyze the signals of the 2560 calorimeter trigger tower samples and construct trigger primitives in /spl sim/3 /spl mu/s at a rate of 7.57 MHz. We give a detailed description of the two prototype boards that are being built: the analog-to-digital converter and filter board (ADF) that performs the analog conversion and digital processing of 32 calorimeter channels, and the trigger algorithm board (TAB) designed to run the physics selection algorithms on one eighth of the 480 Gbit/s of data produced by the complete set of ADF boards.