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We develop an accurate analytical expression for the propagation delay of submicrometer CMOS inverters that takes into account the short-circuit current, the input-output coupling capacitance, and the carrier velocity saturation effects, of increasing importance in submicrometer CMOS technologies. The model is based on the nth-power-law MOSFET model and computes the delay from the charge delivered to the gate. Comparison with HSPICE level 50 simulations and other previously published models for a 0.18-μm and a 0.35-μm process technologies show significant improvements over previous models.
Circuits and Systems I: Regular Papers, IEEE Transactions on (Volume:51 , Issue: 7 )
Date of Publication: July 2004