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An analytical charge-based compact delay model for submicrometer CMOS inverters

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2 Author(s)
J. L. Rossello ; Phys. Dept., Balearic Islands Univ., Palma de Mallorca, Spain ; J. Segura

We develop an accurate analytical expression for the propagation delay of submicrometer CMOS inverters that takes into account the short-circuit current, the input-output coupling capacitance, and the carrier velocity saturation effects, of increasing importance in submicrometer CMOS technologies. The model is based on the nth-power-law MOSFET model and computes the delay from the charge delivered to the gate. Comparison with HSPICE level 50 simulations and other previously published models for a 0.18-μm and a 0.35-μm process technologies show significant improvements over previous models.

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IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:51 ,  Issue: 7 )