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Operator headcount optimization through VLSI test process simulator with human factor

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3 Author(s)
Matsuo, T. ; Dept. of Inf. Syst. Eng., Osaka Univ., Suita, Japan ; Nakamae, Koji ; Fujioka, Hiromu

We have tried to optimize operator headcounts in the final test process of a one-chip microcomputer using a VLSI test process simulator with human factor to reply to an employment issue of how many new workers should be hired. The assumed final test process of a one-chip micro-computer has nine test flows that consists of fourteen stages at most. We select tasks for change kit exchanges and machine troubles as those required for a learning process. We simulate the work performance of newly hired workers by using the hyperbolic function with three parameters as a functional model of individual learning. According to the work performance value, we divide the learning process into three stages. The learning process for each stage differs according to relationships with expert workers. Our implemented event-driven simulator includes both processing-related and cost-related parameters. Simulations for two years were carried out for about total 2,400 lots/month. Result suggests that the manufacturing manager should hire new workers so that the ratio between newly hired and expert workers is about 1:2.

Published in:

Advanced Semiconductor Manufacturing, 2004. ASMC '04. IEEE Conference and Workshop

Date of Conference:

4-6 May 2004