By Topic

Yield learning using the defect reticle method

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Neyer, T. ; Yield Enhancement Projects PL VI, Infineon Technol., Villach, Austria ; Hafner, M.

In this paper we describe a technique called the defect reticle method and illustrate its application to semiconductor manufacture. This technique sheds light on many unknown and so far inaccessible relationships between defect types and yield loss. We discuss an excerpt of results from the first year of application of this method within Infineon.

Published in:

Advanced Semiconductor Manufacturing, 2004. ASMC '04. IEEE Conference and Workshop

Date of Conference:

4-6 May 2004