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Trimming of hard-masks by gaseous Chemical Oxide Removal (COR) for sub-10 nm gates/fins, for gate length control and for embedded logic

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24 Author(s)
Natzle, W.C. ; Microelectron. Div., IBM Semicond. Res. & Dev. Center, Hopewell Junction, NY, USA ; Horak, D. ; Deshpande, S. ; Chien-Fan Yu
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A method for formation and control of silicon gates or fins uses trim of a hard mask by a new gaseous oxide etch. The method decouples final feature size from lithography and from the RIE resist trim/oxide mask open processes. Logic blocks with two separately controlled gate lengths and dielectric thicknesses are embedded on chip. COR control has achieved final size sprads of 1 to 2 nm using measurements from either the factory CDSEM or from a scatterometer integrated on the process tool.

Published in:

Advanced Semiconductor Manufacturing, 2004. ASMC '04. IEEE Conference and Workshop

Date of Conference:

4-6 May 2004

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