Overcoming the challenges in thin wafer (≤8 mils) manufacturing

In this paper effective manufacturing of power discrete devices on thinned (≤8 mils or ∼200 μm) 200 mm substrates will be discussed. The findings in this study can also be applied to integrated circuit technologies. Most of the challenges occur in the back end of line (BEOL) where the substrate thinning typically is performed; therefore issues in this area will be discussed. The other key areas that will be discussed are substrate issues, wafer handling issues, and equipment & tool issues. The overall goal will be to highlight challenges in each area and denote possible or existing resolutions that enable high yield and low breakage manufacturing.