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Interconnection parasitic capacitance is the dominant delay and noise source in modem integrated circuits. Intra-layer capacitance plays a more and more important role in advanced technologies due to tighter pitch and higher aspect ratios. This study presents a novel test structure and a two-step method for measuring intra-layer coupling capacitance Cc, based on a charge-based capacitance measurement technique, which consumes less wafer area and gives a simple method and a high-resolution extraction of intralayer capacitance parameters. The comparison of Cc between measurement and simulation results shows good agreement, with a difference of less than 5%.