By Topic

Method of and test structures for measuring intra-layer coupling capacitance based on charge based capacitance measurement technique [IC interconnections]

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Kai-Ye Huang ; Winbond Electron. Corp., Hsinchu, Taiwan ; Chuan-Jane Chao

Interconnection parasitic capacitance is the dominant delay and noise source in modem integrated circuits. Intra-layer capacitance plays a more and more important role in advanced technologies due to tighter pitch and higher aspect ratios. This study presents a novel test structure and a two-step method for measuring intra-layer coupling capacitance Cc, based on a charge-based capacitance measurement technique, which consumes less wafer area and gives a simple method and a high-resolution extraction of intralayer capacitance parameters. The comparison of Cc between measurement and simulation results shows good agreement, with a difference of less than 5%.

Published in:

Microelectronic Test Structures, 2004. Proceedings. ICMTS '04. The International Conference on

Date of Conference:

22-25 March 2004