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Design guide and process quality improvement for treatment of device variations in an LSI chip

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3 Author(s)
M. Aoki ; Semicond. Technol. Acad. Res. Center, Yokohama, Japan ; S. Ohkawa ; H. Masuda

We propose guidelines for LSI-chip design, taking the within-die variations into consideration, and for process quality improvement to suppress the variations. The autocorrelation length, λ, of device variation is shown to be a useful measure to treat the systematic variations. We may neglect the systematic variation in chips within the range of λ, while σ2 of the systematic variation must be added to σ2 of the random variation outside the λ. The random variations, on the other hand, exhibit complete randomness even in the closest pair transistors. This implies the traditional "closest possible layout" is no longer meaningful for balancing transistor pairs, and requires careful choice of gate size in designing a transistor pair with a minimum size, such as transfer gates in an SRAM cell. Poly-Si gate formation is estimated to be the most important process to ensure the special uniformity in transistor current and to enhance circuit performance.

Published in:

Microelectronic Test Structures, 2004. Proceedings. ICMTS '04. The International Conference on

Date of Conference:

22-25 March 2004