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Electrostatic discharge (ESD) is a major reliability concern for semiconductors. The product qualification tests for ESD human body model (HBM), machine model (MM), and charged device model (CDM) - are good predictors of susceptibility to ESD, but they are not useful tools during the design of ESD protection circuits. Transmission line pulse (TLP) measurements have become an important tool in the design of on-chip protection. This paper will discuss ESD for semiconductor products, review the product qualification tests (HBM, MM, and CDM), and show how TLP measurements can be used to improve the design process for ESD on-chip protection.