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A device design methodology for sub-100-nm SOC applications using bulk and SOI MOSFETs

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3 Author(s)
Suryagandh, S.S. ; Dept. of Electr. Eng., Univ. of California, Los Angeles, CA, USA ; Garg, M. ; Woo, J.C.S.

CMOS for the mixed-mode applications has gained much interest recently. While the International Technology Roadmap for Semiconductors provides two different scaling guidelines for the analog and digital circuit operation using the bulk MOSFET, there are no well-defined scaling guidelines for improving the analog performance of silicon-on-insulator (SOI) MOSFETs. This paper presents a systematic and quantitative comparison between the analog characteristics of the bulk and SOI technology. The intrinsic gain, fT and gm/Ids ratio are considered as a metric for this comparison. It is shown that, even for the operating frequencies in the range of gigahertz (where the ac kink effect is suppressed), analog performance of SOI devices is inferior to that of the bulk devices due to the capacitive drain-to-body coupling. Based on our study, we show that hat the gate-workfunction engineering (close to mid-gap workfunction) is essential in fully depleted SOI (FDSOI) devices for improving analog performance. The analog performance of partially depleted SOI (PDSOI) devices can be improved by using body-tied structures. An increased gate control in double-gate MOSFETs can provide very high output resistance for short-channel devices.

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Electron Devices, IEEE Transactions on  (Volume:51 ,  Issue: 7 )