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Flip chip assembly of die onto a substrate has been in existence since the 1960's. Today there is a great deal of interest in flip-chip technology, especially its use in chip scale packaging (CSP), where it has seen dramatic take-up in the mobile phone and display markets. Due to the continued drive to add further functionality to these products the trend in flip-chip interconnects is towards an ever finer pitch providing more I/O per square area of die. This trend is posing a number of challenges to package designers and board assemblers in terms of reliability. This paper discusses the results from a project investigating the manufacture and reliability of flip-chip interconnects at sub 100 micron pitch.