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Parallel algorithms for minimizing multiple-valued programmable logic arrays

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2 Author(s)
Tirumalai, P.P. ; Hewlett-Packard Lab., Palo Alto, CA, USA ; Vadakkencherry, V.G.

Two versions of a minimization algorithm for multiple-valued programmable logic arrays for shared and distributed memory multiprocessor systems are presented. Both algorithms exploit the considerable parallelism available in the minimization problem. Discussed are communication, synchronization, and load balancing issues under the two machine models. Limited access and the cost of the required computation prevented running of the two parallel algorithms on the actual machines; however, it was possible to run parallel algorithms for a different, but very similar, problem that required less computation. These results indicate that excellent speedups, in some cases superlinear (i.e, more than the number of processors), can be obtained from parallel implementations of this logic minimization algorithm

Published in:

Multiple-Valued Logic, 1991., Proceedings of the Twenty-First International Symposium on

Date of Conference:

26-29 May 1991