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Deep sub-micron ultra-low power CMOS device design and optimization

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6 Author(s)
Xinfu Liu ; Serydconductor Manuf. Int. Corp., Shanghai, China ; K. Y. Wu ; Jianghua Ju ; Hokmin Ho
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In this work, CMOS devices with very low leakage current (Ioff) are studied for Ultra Low Power (ULP) applications. The ULP is targeted for worst-case Ioff <0.5 pA/μm. We used our 0.15 μm and 0.18 μm base line process to optimize the Vt, LDD, pocket and S/D implant to reduce device GIDL, poly edge junction leakage, band to band leakage and DIBL. A ULP product, CMOS I Mbit SRAM with measured minimum standby current < 10 μA were fabricated successfully.

Published in:

Junction Technology, 2004. IWJT '04. The Fourth International Workshop on

Date of Conference:

15-16 March 2004