Skip to Main Content
In this work, CMOS devices with very low leakage current (Ioff) are studied for Ultra Low Power (ULP) applications. The ULP is targeted for worst-case Ioff <0.5 pA/μm. We used our 0.15 μm and 0.18 μm base line process to optimize the Vt, LDD, pocket and S/D implant to reduce device GIDL, poly edge junction leakage, band to band leakage and DIBL. A ULP product, CMOS I Mbit SRAM with measured minimum standby current < 10 μA were fabricated successfully.