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An optimised approach to MPEG layer-3 (MP3) audio decoding is presented, with the main theme focused on the synthesis subband. Since the synthesis subband is the most power-consuming component in decoding, a cost-effective architecture is proposed based on a system-design consideration. By means of an algorithm and architecture, the synthesis subband achieves a high throughput with reduced memory requirements and hardware complexity. With a two-stage pipeline architecture, it allows 100% hardware utilisation and is suitable for low-power implementation. In addition, the chip design in a 0.35 μm process is also accomplished. It occupies a die area of about 2.7 × 3.2 mm2 with a transistor count of 157469 and a low-power dissipation of only 2.92 mW.