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Novel numerical and experimental analysis of dynamic responses under board level drop test

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5 Author(s)
Tong Yan Tee ; STMicroelectronics, Singapore, Singapore ; Jing-en Luan ; Eric Pek ; Chwee Teck Lim
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Board level solder joint reliability during drop test is a great concern to semiconductor and electronic product manufacturers. A new JEDEC standard for board level drop test of handheld electronic products was just released to specify the drop test procedure and conditions. In this paper, comprehensive dynamic responses of PCB and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed in detail with a multi-channel real-time electrical monitoring system. It is found experimentally and numerically that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint fatigue failure. A novel input acceleration (input-G) method is developed to simulate the exact drop test process using ANSYS-LSDYNA software. The model can be applied to simulate the overall impact responses including PCB cyclic bending, which are very critical for understanding of board level drop test.

Published in:

Thermal and Mechanical Simulation and Experiments in Microelectronics and Microsystems, 2004. EuroSimE 2004. Proceedings of the 5th International Conference on

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