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Using layout technique and direct-tunneling mechanism to promote DC performance of partially depleted SOI devices

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3 Author(s)
Shiao-Shien Chen ; Device Eng. Dept., United Microelectron. Corp., Hsinchu, Taiwan ; Shiang Huang-Lu ; Tien-Hao Tang

This paper reports the dc performance enhancements of partially depleted (PD) silicon-on-insulator (SOI) devices with lower subthreshold swing and higher driving capability, kink-onset voltage, and transconductance simultaneously. Based on the measured results, by using layout technique, for floating-body PD SOI pMOSFETs with ultrathin gate-oxide thickness, H-gate configuration with the partial n+ poly-gate shows the best floating-body characteristics as compared to that in T-gate and three-terminal configurations. Owing to the direct-tunneling mechanism in the partial n+ poly-gate, the conduction-band electron tunneling current will make the floating-body potential biased in strong inversion region raised. In addition, due to the larger oxide voltage drop across the partial n+ poly-gate in subthreshold region, the valence-band hole substrate current will result in lower floating-body potential. These dc performance enhancements advantage in both digital and analog designs.

Published in:

Electron Devices, IEEE Transactions on  (Volume:51 ,  Issue: 5 )

Date of Publication:

May 2004

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