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A nanoscale memory and transistor using backside trapping

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2 Author(s)
Silva, H. ; Sch. of Appl. & Eng. Phys., Cornell Univ., Ithaca, NY, USA ; Tiwari, S.

We report results on a new structure that provides a scalable memory cell and a scalable transistor simultaneously in the same structure. The operational distinction is achieved through a difference in the bias range. The device employs a modified silicon-on-insulator substrate where charge is stored in a defected region underneath a thin single-crystal silicon layer employed for the formation of the transistor channel. At low voltages (below 1.5 V), the device operates as a transistor making use of the front silicon interface (preferred form), or the back interface, or both. The memory operation is obtained by use of high voltages, which allow injection of charge into the defected region in a stack of insulating films underneath the thin silicon channel, as well as the removal of the charge. The transistors are scalable because of the thin silicon technology and the memories are highly scalable because they allow efficient coupling between the carriers and storage region. The structure provides for a very useful decoupling of the memory read and transistor operation from the memory electrical storage operation. The experimental operation of the devices is described.

Published in:

Nanotechnology, IEEE Transactions on  (Volume:3 ,  Issue: 2 )