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Scalable scheduling architectures for high-performance crossbar-based switches

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4 Author(s)
Jing Liu ; Dept. of Comput. Sci., Hong Kong Univ. of Sci. & Technol., Kowloon, China ; Hamdi, M. ; Qingsheng Hu ; Tsui, C.Y.

This paper presents a novel scalable scheduling architecture for high-performance crossbar-based switches with virtual output queuing (VOQ) scheme. In contrast to traditional switching architectures where the scheduler is implemented by one single centralized scheduling device, the proposed scheduling architecture connects several small scheduling devices in series and the arbitration algorithm is executed in parallel. Thereby the inputs of each single scheduling device establish connections to a group of outputs, by considering both their local transmission requests as well as global output availability information. The advantage of this architecture lies in its ability to implement large schedulers (> 64) with several small scheduling devices as well as in its capability to achieve high-performance scheduling. We first introduce a distributed parallel round robin scheduling algorithm (DPRR) for the proposed architecture. Through the analysis of simulation results on various admissible traffics, it is shown that the performance of DPRR is much better than the performance of other round robin scheduling algorithms commonly used on centralized schedulers. We also prove that under Bernoulli i.i.d. uniform traffic, DPRR achieves 100% throughput. Moreover, we introduce a distributed parallel round robin scheduling algorithm with memory (DPRRM) as an improved version of DPRR to make it stable under any admissible traffic.

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High Performance Switching and Routing, 2004. HPSR. 2004 Workshop on

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