Skip to Main Content
Summary form only given. The architecture of modern FPGAs contain over one thousand small memory banks, over five hundred 4k-bit memory banks, and over one hundred thousand logic elements. This inherent parallelism of an FPGA makes it an ideal platform for a multiprocessor architecture. In addition to embedded memory, numerous ASIC multipliers are embedded into the FPGA architecture. This paper introduces a single-instruction-multiple-data (SIMD) system comprised of 2, 4, 8, 16, 32, 64 and 88 processing elements that are built around the ASIC multipliers and controlled by a central instruction stream. In addition to the function of the ASIC multiplier, we have augmented each PE with "custom instructions" to show how the instruction set can be extended. The 88 processors SIMD design utilizes 100% of the DSP blocks available in the Altera Stratix EPS80F1508C6 device, but only 17% of the look-up table logic, which leaves 83% of the logic cells available for custom instructions.