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Area optimization of delay-optimized structures using intrinsic constraint graphs

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3 Author(s)
Peyran, O. ; Inst. of High Performance Comput., Singapore ; Zheng Zeng ; Wenjun Zhuang

In this paper, we present a new methodology for structure optimization of block-based design. Instead of merging area and delay criteria, we segregate them into two independent steps. Solutions optimized for delay in the first step are optimized for area with a block-sizing algorithm in the second step. The fully optimized solutions eventually return to the first optimization step, if the user constraints are not met, using a structure-extraction module. A condition to this approach is that the area optimization phase does not alter the quality reached during delay optimization. We propose a framework for area optimization of delay-optimized structures based on structure similarities. We present a new model to represent block placements that share the same qualities for global routing. Using this model, we formally define the relation of similarity and exhibit several properties and theorems to validate our approach. The modules composing the area optimization phase are presented and experimental results confirm the validity of our methodology.

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:23 ,  Issue: 6 )