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DFT for delay fault testing of high-performance digital circuits

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3 Author(s)
Chatterjee, B. ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; Sachdev, M. ; Keshavarzi, A.

Timing-only parametric defects are a major source of failures and test escapes in modern ICs. A DFT technique using compound domino logic gates with footer transistors uncovers these hard-to-detect defects with minimal performance and power overheads.

Published in:

Design & Test of Computers, IEEE  (Volume:21 ,  Issue: 3 )