By Topic

A method to diagnose faults in analog integrated circuits using artificial neural networks with pseudorandom noise as stimulus

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
L. Barua ; Dept. of Electr. Eng., Indian Inst. of Technol., Kharagpur, India ; P. Kabisatpathy ; S. Sinha

This paper describes a new, fast and economical strategy for fault diagnosis of analog integrated circuits. The methodology is based on a technique of using a pseudo random noise generator as the test pattern generator and a model-based observer, which is implemented through a feed forward artificial neural network in the form of a single hidden-layer perceptron. The proposed methodology can be implemented in any personal computer with a data acquisition card for on-line operation. Its main advantages are the low time requirement for learning and diagnosing. The method is quite robust and is able to detect small component variations without problems. This technique has been successfully applied to diagnose both hard and soft faults in a bipolar junction transistor based operational amplifier and a MOS operational amplifier.

Published in:

Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on  (Volume:1 )

Date of Conference:

14-17 Dec. 2003