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A 5GHz CMOS digitally controlled oscillator with a 3GHz tuning range for PLL applications

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1 Author(s)
S. M. R. Hasan ; Dept. of Electr. & Comput. Eng., Univ. of Shaljah, Sharjah, United Arab Emirates

A 16-bit digitally controlled CMOS oscillator (DCO) is described. This CMOS DCO design provides improved phase noise characteristics. Simulations of a 4-stage DCO using a 0.18μm TSMC CMOS process parameters achieved a controllable frequency range of 1.78GHz - 4.8GHz with a monotone tuning range of around 3GHz. Worst-case jitter due to digital control transitions at pathological control-word boundaries for the CMOS DCO was observed to be less than 100 ps. This CMOS design would thus provide considerable performance enhancement in digital PLL applications.

Published in:

Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on  (Volume:1 )

Date of Conference:

14-17 Dec. 2003