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A protection mechanism for intellectual property rights (IPR) in FPGA design environment

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3 Author(s)
W. Adi ; Etisalat Coll. of Eng., Ajman Univ. of Sci. & Technol., United Arab Emirates ; B. Soudan ; N. Kassab

One of the major difficulties in offering new VLSI designs is protecting the designer's intellectual property rights (IPR). It often requires limited field deployment and testing before a novel implementation may be accepted for general use. The difficulty arises in the need to deploy the design for testing while disabling the tester from deciphering the design details. A similar requirement applies when the designer is interested in limiting the number of deployments as part of a business agreement. This work leverages the similarities between the issues of IPR protection in the hardware and software arenas and presents a novel solution to protect the use of designs in the FPGA hardware environment. The mechanisms used are based on hardware-supported design encryption and secured authentication protocols.

Published in:

Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on  (Volume:1 )

Date of Conference:

14-17 Dec. 2003