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68040 memory modules and bus controller

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3 Author(s)
B. Martin ; Motorola Inc., Austin, TX, USA ; S. McMahan ; L. Sood

The 68040 processor includes an instruction memory system, a data memory system, and a synchronous bus. These resources are controlled by three autonomous machines, the instruction memory controller (IMEMC), the data memory controller (DMEMC), and the bus controller (BC). The structure of the data paths, the main caches, the address-translation caches, and the controllers are presented, including a discussion of the methodologies used in the development

Published in:

Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on

Date of Conference:

17-19 Sep 1990