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Low power high speed I/O interfaces in 0.18 μm CMOS

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2 Author(s)
Y. Yan ; Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, Ont., Canada ; T. H. Szymanski

The design and implementation of a low power high speed differential signaling input/output (I/O) interface in 0.18 μm CMOS technology is presented. The motivations for smaller signal swings in transmission are discussed. The prototype chip supports 4 Gbps data rate with less than 10 mA current at 1.8 V supply according to Cadence Spectre post-layout simulations. Performance comparisons between the proposed device and other signaling technologies reported recently are given.

Published in:

Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on  (Volume:2 )

Date of Conference:

14-17 Dec. 2003