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Built-in self-test with weighted random pattern hardware

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3 Author(s)
F. Brglez ; Microelectron. Center of North Carolina, Research Triangle Park, NC, USA ; G. Gloster ; G. Kedem

The authors address scan-based built-in self-test (BIST) of digital circuits that are highly resistant to testing with uniform random patterns. Introducing a procedure, the precompute test patterns for random-pattern resistant faults and generate optimized distributions of weights that guarantee pattern coverage in a given number of random trials. The software implementation offers a tradeoff in the number of distributions (hardware memory) and the length of the total test time. The hardware implementation is based on a canonic weighting circuit that interfaces to a circulating memory and a pseudo-random source

Published in:

Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on

Date of Conference:

17-19 Sep 1990