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A compact, low power, clock frequency doubler circuit with no external devices designed and manufactured in a 0.5μm CMOS technology. Proposed circuit generates a 4.096MHz output clock frequency from a 2.048MHz input clock while an automatic duty cycle control circuit reduces the sensitivity of the duty cycle of output clock to the duty cycle of input signal or process and temperature variations. For this purpose, an accurate delayed clock is generated. Very simple structure besides MOSFET capacitors offers a compact and low power circuit. The area of the circuit is 0.08mm2 while consumes 380μArms from 5V power supply and drives 15pF capacitor load. Measured output duty cycle shows a variance of 2.7% from the desired nominal value.