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The design of a RISC based multiprocessor chip

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3 Author(s)
Gupta, R. ; Dept. of Comput. Sci., Pittsburgh Univ., PA, USA ; Epstein, M. ; Whelan, M.

The architecture of an RISC (reduced instruction set computer) based on multiprocessor chip designed in the Briarcliff Multiprocessor Project is described. The processors operate in an MIMD (multiple instruction, multiple data) fashion, executing parallel instruction streams generated by a parallelizing compiler for the exploitation of fine-grained parallelism. Low-cost synchronization mechanisms are supported in hardware. The resulting system is tolerant of unpredictable delays in the progress of individual streams. Instruction level parallelism is exploited through the use of register channels and a mechanism for the collective branching of processors. For efficient synchronization during parallel execution of loops, fuzzy barriers are provided. On-chip memory is organized into multiple banks in order to provide sufficient bandwidth for the processors. The RISC processors are based upon the Sun SPARC architecture

Published in:

Supercomputing '90., Proceedings of

Date of Conference:

12-16 Nov 1990