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Timing jitter is a concern in high frequency oscillators; the presence of timing jitter will degrade system performance in many high speed applications. In the first part of the paper, the authors have simulated the timing jitter due to CMOS device noise in a nine-stage CMOS differential ring oscillator, and a methodology to efficiently simulate timing jitter has been developed. Simulation results show that the variation of absolute jitter due to flicker noise has t-dependence while for white noise it has t0.5-dependence; these are consistent with accepted theory. Two important parameters, cycle jitter and cycle-to-cycle jitter, used to describe jitter performance can be obtained from simulation. Simulation results are also compared with measurement results, and it is shown that simulation results are very close to measurement results. All these serve to verify the validity of this technique. In the second part of the paper, the authors have employed this methodology and investigated the timing jitter in silicon BJT/or SiGe HBT ECL ring oscillators, and they have shown that BJT/or SiGe HBT oscillators have lower jitter compared to their CMOS counterparts. The methodology described in the paper is also applicable to other types of clock generator and oscillators such as LC oscillators, as well as other kinds of noise source such as power supply and substrate noise.