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Fermi-level pinning at the polysilicon/metal oxide interface-Part I

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20 Author(s)
C. C. Hobbs ; Technol. Solutions Group, Motorola, Austin, TX, USA ; L. R. C. Fonseca ; A. Knizhnik ; V. Dhandapani
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We report here that Fermi pinning at the polysilicon/metal oxide interface causes high threshold voltages in MOSFET devices. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO2 and Al2O3, respectively. Oxygen vacancies at polysilicon/HfO2 interfaces also lead to Fermi pinning. We show that this fundamental characteristic affects the observed polysilicon depletion. In Part I, the theoretical background is reviewed and the impact of the different gate stack regions are separated out by investigating the relative threshold voltage shifts of devices with Hf-based dielectrics. The effects of the interfacial bonding are examined in Part II.

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IEEE Transactions on Electron Devices  (Volume:51 ,  Issue: 6 )