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Cache coherence in systems with parallel communication channels and many processors

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3 Author(s)
Willis, J.C. ; Philips Lab., Briarcliff Manor, NY, USA ; Sanderson, A.C. ; Hill, C.R.

The authors describe and analyze two algorithms for maintaining cache coherence in multiprocessor systems with parallel communication channels and many processors. A distributed link-list relates all cache frames representing the same main memory block. Messages traverse the list to maintain list integrity, exclusive ownership, and consistent values. Memory access semantics are equivalent to a shared memory system without caches. Reference latency, efficiency of memory use, and hardware complexity are moderate and well-bounded. A brief comparison with the Scalable Coherent Interface illustrates some of the design tradeoffs associated with distributed directory algorithms

Published in:

Supercomputing '90., Proceedings of

Date of Conference:

12-16 Nov 1990