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A distributed colouring algorithm for control hazards in asynchronous pipelines

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2 Author(s)
T. Theodoropoulos ; Sch. of Comput. Sci., Birmingham Univ., UK ; Qianyi Zhang

Synchronous VLSI design is approaching a critical point, with clock distribution becoming an increasingly costly and complicated issue and power consumption rapidly emerging as a major concern. Hence, recently, there has been a resurgence of interest in asynchronous digital design techniques as they promise to liberate VLSI systems from clock skew problems, offer the potential for low power and high performance and encourage a modular design philosophy which makes incremental technological migration a much easier task. In a pipelined architecture, if a control hazard occurs, the prefetched instructions following a hazard must be discarded and removed from the pipeline before instructions from the new stream are executed. In an asynchronous microprocessor the exact number of the prefetched instructions is nondeterministic and unpredictable. The processor must be able to distinguish between instructions originating from the branch or the exception target, which may thus be executed, and instructions already prefetched when the hazard took place, which must therefore be thrown away. This paper discusses a distributed, asynchronous technique for dealing with control hazards in asynchronous pipelines where control hazards may potentially occur in more than one stage.

Published in:

Parallel Architectures, Algorithms and Networks, 2004. Proceedings. 7th International Symposium on

Date of Conference:

10-12 May 2004