By Topic

Processor mapping technique for communication free data redistribution on symmetrical matrix

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Ching-Hsien Hsu ; Dept. of Comput. Sci. & Inf. Eng., Chung Hua Univ., Hsinchu, Taiwan ; Kun-Ming Yu

In this paper, we present the processor mapping technique to eliminate amount of data exchange in runtime data redistribution on symmetric matrices. The main idea of the proposed technique is to develop mathematical functions for mapping destination processors to a new sequence of processor id. The realigned order of destination processors is then used to perform data redistribution in the receiving phase. Together with a local matrix transposition scheme, interprocessor communication can be totally eliminated in runtime redistribution. The other improvement of this approach is that one does not need to compute the complicated communication sets. The indexing cost is reduced largely. The theoretical analysis shows that (p-1)/p data transmission cost can be saved for a redistribution over p×p processors grid. Experimental result also shows that the processor mapping technique provides superior improvement for runtime data redistribution.

Published in:

Parallel Architectures, Algorithms and Networks, 2004. Proceedings. 7th International Symposium on

Date of Conference:

10-12 May 2004