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Multi-level logic optimization for large scale ASICs

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4 Author(s)
Nagoya, A. ; NTT Commun. & Inf. Process. Lab., Kanagawa, Japan ; Nakamura, Y. ; Oguri, K. ; Nomura, R.

The authors developed an efficient high-level synthesis and optimization system for large-scale circuits, which reduces the total number of fan-ins in the technology-independent phase and adjusts speed and area after technology mapping is completed. A description is presented of multi-level logic optimization techniques based on refined weak division methods and additional functions for carrying out good optimization with only a slight overhead. The authors also describe technology mapping and local optimization techniques suitable for high-level CAD systems. The system has shown that multi-level logic optimization in VLSIs with more than 100000 gates (that is, VLSIs whose control logic comprises more than 10000 gate circuits) is possible in practical CPU time.<>

Published in:

Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on

Date of Conference:

11-15 Nov. 1990

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