By Topic

VLSI circuit design using an object-oriented framework of evolutionary graph generation system

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Homma, N. ; Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan ; Natsui, M. ; Aoki, T. ; Higuchi, T.

This paper presents a generic objected-oriented framework of evolutionary graph generation (EGG) for automated circuit synthesis. The EGG system can be systematically implemented for different design problems by inheriting the framework class templates. The potential capability of EGG framework is demonstrated through experimental synthesis of both digital and analogue circuits. Design examples discussed in this paper are: (i) bit-serial multipliers using bit-level arithmetic components; and (ii) current mirrors using transistor-level components.

Published in:

Evolutionary Computation, 2003. CEC '03. The 2003 Congress on  (Volume:1 )

Date of Conference:

8-12 Dec. 2003