VLSI circuit design using an object-oriented framework of evolutionary graph generation system

This paper presents a generic objected-oriented framework of evolutionary graph generation (EGG) for automated circuit synthesis. The EGG system can be systematically implemented for different design problems by inheriting the framework class templates. The potential capability of EGG framework is demonstrated through experimental synthesis of both digital and analogue circuits. Design examples discussed in this paper are: (i) bit-serial multipliers using bit-level arithmetic components; and (ii) current mirrors using transistor-level components.