By Topic

Exploitation of instruction-level parallelism for optimal loop scheduling

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Muller, J. ; Dept. of Electr. Eng., Dresden Univ. of Technol., Germany ; Fimmel, D. ; Merker, R.

We present a loop scheduling approach which optimally exploits instruction-level parallelism. We develop a flow graph model for the resource constraints allowing a more efficient implementation. The method supports heterogeneous processor architectures and pipelines functional units. Our linear programming implementation produces an optimum loop schedule, making the technique applicable to production compilation and hardware parametrization. Compared to earlier approaches, the approach can provide faster loop schedules and a significant reduction of the problem complexity and solution time.

Published in:

Interaction between Compilers and Computer Architectures, 2004. INTERACT-8 2004. Eighth Workshop on

Date of Conference:

15 Feb. 2004