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To enable optimizations in memory access behavior of high performance applications, cache monitoring is a crucial process. Simulation of cache hardware is needed in order to allow research for non-existing cache architectures, and on the other hand, to get more insight into metrics not measured by hardware counters in existing processors. One focus of EP-Cache, a project investigating efficient programming on cache architectures, is on developing cache monitoring hardware to give precise information about the cache behavior of OpenMP applications on SMP machines. As the hardware is still in an early state of development, getting experience with the monitoring software infrastructure to be built for use in real applications requires cache simulation. Two techniques are used for the cache simulation engine: driven by instrumentation integrated at source level and instrumentation integrated at runtime by rewriting code on-the-fly. In this paper, we mainly describe the second technique together with a sample code, showing the advantages and feasibility of this approach. Additionally, in order to allow a comparison, we also give a brief description of the experience with the source instrumentation technique.