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Don't care minimization of multi-level sequential logic networks

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3 Author(s)
B. Lin ; California Univ., Berkeley, CA, USA ; H. J. Touati ; A. R. Newton

The authors address the problem of computing sequential don't cares that arise in the context of multi-level sequential networks and their use in sequential logic synthesis. The key to their approach is the use of binary decision diagram (BDD)-based implicit state space enumeration techniques and multi-level combinational simplification procedures. Using the algorithms described, exact sequential don't care sets for circuits with over 10/sup 68/ states have been successfully computed.<>

Published in:

Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on

Date of Conference:

11-15 Nov. 1990