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Data synchronization issues in GALS SoCs

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3 Author(s)
Dobkin, R. ; VLSI Syst. Res. Center, Technion-Israel Inst. of Technol., Haifa, Israel ; Ginosar, R. ; Sotiriou, C.P.

Locally generated, arbitrated clocks for GALS SoCs as stated in S. Moore et al. (April 2002) face the risk of synchronization failures if clock delays are not accounted for. The problem is analyzed based on clock delays, cycle times, and complexity of the asynchronous port controllers. A number of methods are presented. In some cases, it is sufficient to extract all the delays and verify whether the system is susceptible to metastability. In other cases, when high data bandwidth is not required, asynchronous synchronizers or matched-delay asynchronous ports may be employed. Arbitrated clocks may be traded off for locally delayed input and output ports, facilitating high data rates. The latter circuits have been simulated, to verify their performance.

Published in:

Asynchronous Circuits and Systems, 2004. Proceedings. 10th International Symposium on

Date of Conference:

19-23 April 2004

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